A track-and-hold circuit, or sample-and-hold circuit, is a type of circuit that may typically be used in a front end of an analog-to-digital (A/D) converter to sample a continuously varying signal in discrete time intervals. A conventional track-and-hold circuit may typically include a switch and a capacitor. As such, a conventional track-and-hold circuit may exhibit considerable channel charge injection and/or variation in channel conductance, both of which may be dependent on the gate-source voltage and/or the threshold voltage of the switch in the track-and-hold circuit.
FIG. 1 is a circuit diagram illustrating a conventional track-and-hold circuit. Referring to FIG. 1, a n-channel metal-oxide semiconductor (NMOS) transistor 20 functioning as a switch includes a gate terminal to which a pulse signal VP having a given period is applied, a source terminal to which an analog input signal VIN is applied, and a drain terminal coupled to a hold capacitor CH. The track-and-hold circuit may function in a track mode operation and a hold mode operation. In track mode operation, the NMOS transistor 20 is turned on in response to applying the pulse signal VP at a logic ‘high’ level, and the hold capacitor CH is electrically charged. In hold mode operation, the NMOS transistor 20 is turned off in response to applying the pulse signal VP at a logic ‘low’ level, and the hold capacitor CH holds the stored electric charges.
When the NMOS transistor 20 transitions from a turned-on (i.e., conducting) state to a turned-off (i.e., non-conducting) state, electric charges, which may be deposited in a channel region under the gate of the NMOS transistor 20, may be released either to the input voltage terminal or to the hold capacitor CH, with equal likelihood. As such, about a half of the released charges may be transferred to the hold capacitor CH. The formula (½)×(COX×W×L)×(Vgs−Vth) may be used to describe the charges transferred to the hold capacitor CH, where COX denotes capacitance per unit area of a gate oxide layer, W denotes a width of the gate, L denotes a length of the gate, Vgs denotes a voltage between the gate terminal and the source terminal, and Vth denotes the threshold voltage of the NMOS transistor 20.
A channel voltage Vch across the channel of the NMOS transistor 20 may be represented by:Vch=−((COX×W×L)/(2×Chold))×(Vgs−Vth)  Equation 1
wherein Chold denotes a capacitance of the hold capacitor CH.
When the input signal VIN is a sine wave Asin(ωt), the gate-source voltage Vgs may be represented by the formula Vgs=VP−Asin(ωt), wherein A denotes a voltage amplitude of the input signal VIN. A change in the gate-source voltage ΔVgs may be represented by:ΔVgs=A sin(ωt)  Equation 2
The threshold voltage Vth may be represented by:Vth=Vtho+Γ×[(2φF+VSB)1/2−(2φF)1/2]  Equation 3
wherein Vtho denotes an initial threshold voltage, φF denotes a work function, VSB denotes a voltage between the source and a body of the transistor, and Γ denotes (2qεSNSUB)1/2/COX, wherein q denotes an amount of electric charge of an electron, εS denotes a permittivity of silicon, and NSUB denotes a doping concentration of a substrate (or the body).
A change in the threshold voltage ΔVgs may be represented by:ΔVth=Γ×[A sin(ωt)]1/2  Equation 4
Referring to equations 1, 2 and 4, a maximum change in voltage ΔVch,var for the channel voltage Vch, based on the charge injection, may be represented by:ΔVch,var=[(COX×W×L)/(2×Chold)]×[A+Γ×A1/2]  Equation 5
Accordingly, as the gate-source voltage Vgs and the threshold voltage Vth vary in response to the input signal VIN, the maximum change in the channel voltage ΔVch,var may be varied based on the input signal VIN.
When an NMOS transistor operates in the linear region, a drain current id of the NMOS transistor can be represented by the formula id=Kn/2[2(Vgs−Vth)Vds−Vds2], and a channel conductance Gds can be represented by the formula Gds=(∂id/∂vds)≈Kn×(Vgs−Vth), wherein vds denotes a voltage between the drain and the source, Kn denotes μ×COX×W/L and μ denotes an electron mobility. A maximum change in conductance ΔGds,var of the channel conductance Gds may be represented by:ΔGds,var=Kn×[A+Γ×A1/2]  Equation 6
Accordingly, the maximum change in channel conductance ΔGds,var, as well as the maximum change in channel conductance ΔVch,var may be varied depending on the input signal VIN, as the gate-source voltage Vgs and the threshold voltage Vth may vary in response to the input signal VIN.